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You will build a JFET switch, memory cell, current source, and source follower. Remember to keep your parts, do not lose them and do not return them to the parts cabinet. All parts spec sheets are located on the Physics Library site.
What is the maximum allowed gate current? What happens if this current is exceeded? In a few sentences, explain how a self-biased current source works. Explain how to use load line analysis as outlined in the background materials. Why does it give the equilibrium current for the self-biased current source? Refer to the discussion in 4. Why does this degrade the performance of a source follower? Do not forward bias the JFET gates.
The physical mechanisms underlying the operation of these two types of transistors are quite different. We will limit our study to FETs because their physical mechanism is simpler. Transistors are amplifiers; a small signal is used to control a larger signal. Typical transistors have three leads; in the case of a JFET, a voltage on one lead called the gate is used to control a current between two other leads called the source and the drain. Of course, the gate voltage needs to be referenced to some other potential.
By convention, it is referenced to the source. JFETs are drawn as shown to the right where the gate, drain and source G, D, S, respectively labels are normally omitted. Transistor voltages and currents are labeled by subscripts referring to the appropriate lead. Under normal operating conditions, no current flows into the gate. Under normal operating conditions, the JFET gate is always negatively biased relative to the source, i. The JFET may burn out if the gate is positively biased.
This simple picture is the origin of the names for the leads. The pinch-off voltage is sometimes called the cutoff voltage.
A typical plot of the current vs. Simple models of JFET performance predict that the curve will be parabolic, particularly near the pinch-off voltage, but actual devices may differ substantially from this prediction. JFETs are usually, but not always used in the saturation region, and the next two models model this regime only.
We call the JFET in this model ideal because we pretend that its transconductance is infinite. Figure 7: Source resistance model Figure 8: Source resistance Model Equivalence The transconductance model and the source-resistance model are both small signal, i. Though it may not be immediately obvious, they are formally equivalent.
You will sometimes see the archaic, but much more amusing unit, the mho ohm backwards for conductance. Since the models are equivalent, they will give the same results in any circuit. Personally, I JF find the source-resistance model easier to use.
Self-Biased Current Sources Current sources are very important in modern circuit design. A typical operational amplifier op amp , a very common circuit that we will study extensively, might contain a dozen current sources. The behavior of this circuit is not obvious. The circuit depends on feedback: the output of the circuit controls its input. Feedback is an extraordinarily useful and general circuit design technique that has almost magical power.
Let us consider how the above current source might startup when power is first applied. As the current increases, a voltage drop will develop across the resistor, and the upper end of the resistor will become positively biased relative to ground. This means that the gate will become negatively biased with regards to the source.
In sum, the circuit regulates its output by feeding back a signal proportional to its output in this case, the voltage across the resistor into its input.
In turn, this feedback to the input regulates the output. The equilibrium current through the JFET, i. Why does the load line graph have a negative slope? Hence the negative sign. In analogy with the diode load line analysis, the JFET characteristic and the load line must be satisfied simultaneously. Why is this current source stiff? Then consider how the equilibrium point changes. If the load line has a small slope, the changes in the characteristic curve will primarily move the intersection point horizontally.
Consequently, the source will be stiff. Source Followers A follower is a circuit whose output voltage equals its input voltage.
Since followers have no voltage gain, it might appear that they are useless. A particular type of follower, a source follower, can be constructed by slightly modifying a self-biased current source.
Instead of grounding the gate as is done in the current source, the gate is driven by the input signal source as shown at right. The model reduces to a voltage divider driven by a voltage-controlled voltage source as shown at the far right.
Using the model at the far right, we can easily calculate the output impedance of the follower. Packaging and Leads Transistors are manufactured in many different packages and sizes. Devices starting with 1N are always diodes; devices starting with 2N are always transistors.
As with many devices, the lead diagram depends on the view. A bottom view immediate right looks at the device from the lead side. A top view center right looks at the device from the non-leaded side.
When inserting the JFET into the breadboard, there is no need to squash the leads out horizontally. In fact, doing so will risks accidentally shorting the JFET leads to the metal case.
The source and drain can be exchanged without changing the device behavior. But for simplicity, use should generally use the correct source and drain leads. Asymmetric JFETs, in which the source and drain cannot be exchanged, are normally drawn with an offset gate lead as shown at right.
Make sure you keep your JFET separate. Build neat circuits with short wire lengths to minimize noise problems. Problem 4. Describe the results of all your measurements. So far, this switch is not very impressive; we could just as well have switched the LED on and off by moving its own lead rather than the JFET gate lead.
Can you still switch the LED? From 3. This internal capacitance is not accessible from the outside of the device, and will vary from device to device. But when the capacitor is negatively charged, the JFET switch will stay off until the capacitor discharges, i. The circuit can be redrawn with a JFET model shown at right outlined in red that includes these effects.
The memory time can be extended by adding an external capacitor. Use a cell phone stop watch for timing. Note that tie capacitance and leakage resistance of the breadboard itself will influence your measured values by lowering the effective gate resistance and increasing the effetive gate capacitance. Hidden from the user, the computer must cycle through all of its memory this way every few milliseconds. Check your circuit before turning the power on; it is easy to burn out the JFET!
Use the scope or another DMM to measure the gate voltage. They are caused by unintended parasitic capacitances. These capacitances may be internal to the device, or result from the leads and wiring hooked up to the device. First find the most negative voltage for which drain current flows through the FET: the pinch-off voltage.
If the current does not depend on the gate voltage, these base-level readings are from the noise floor of the DMM. Find the gate voltage that just starts to increase the current. Then roughly determine the relationship between current and gate voltage by incrementing the gate voltage to zero, recording the current at approximately five points. If you swap the leads as in solution 1 immediately above, you can then rotate the Terminal Block by degrees so that the Terminal Block Source is plugged into the Tracer Drain, and vice versa.
How close is the characteristic to a parabola? Is it at least a parabola over some limited range? Plot all your data, and add the points that you took by hand to the transfer characteristic curve. The 2N JFET is designed to be operated as a switch, and its transfer characteristic is far from ideal.
Take scans in both the linear and saturated regimes. Save this JFET for many of the remaining exercises. Curve Tracer information Problem 4. Plot the transconductance of this JFET. Note that the 2N uses the pin out shown at left.
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